1. Field of the Invention
The invention is generally related to storage of binary signals in semiconductor integrated circuits, and more particularly to programmable circuits such as read only memories (ROM) and gate arrays.
2. Background Information
A need exists today for denser and faster electronic structures for storing binary signals. Conventional techniques for storing information in semiconductor integrated circuits (ICs) include the use of random access memory (RAM), and read only memory (ROM). In particular, ROMs are used to store binary signals in the form of 1 bit per site, in an array of sites where each site is defined as the area near an active element.
A particular prior art ROM 100 is illustrated in FIG. 1. The ROM 100 includes an array of a large number of programmable sites 111, 112, . . . located at and near the crossing of a row conductor (wordline) and a column conductor (bit line). In particular, FIG. 1 illustrates a metal oxide semiconductor (MOS) ROM structure in which an n-channel field effect transistor (FET) as the active element is located at each site.
The ROM 100 is programmed by the IC manufacturer according to a customer's specifications by making or not making an electrical coupling 117 between the drain of a FET 118 and its corresponding bit line 119. The site 111 may therefore represent 1 bit of programmed information. The bit is accessed by first precharging the bit line 119 to a given voltage (normally a voltage near the rail supply voltage of the ROM IC) with the FET 118 being turned "off" so as to present a sufficiently high impedance to develop the given voltage. Then, the voltage on the wordline 110 is raised. The wordline 110 is coupled to the gate of the FET 118. Raising the potential on the wordline 110 will turn "on" the FET 118 by creating a sufficiently low impedance which then discharges the bit line 119 to a different voltage (normally a voltage close to the common return of the ROM IC). The information that has been programmed into the site 111 may then be read at the output as a first logic level if the coupling 117 is present, or a different logic level if the coupling 117 is not present. The above precharge and discharge cycle is repeated for each row of the ROM 100 to read the entire array.
The structure of FIG. 1 described above is known as a NOR-type ROM with metal programmable couplings. Other NOR-type ROMs exist that perform substantially the same function of encoding 1 bit per site, except that the programming step involves making or not making the FET 118 itself, rather than making or not making a metal coupling to the drain of an existing FET. It may be seen, however, that in either situation, one FET is employed to encode 1 bit. In practice, ROM structures of the type shown in FIG. 1 may be manufactured to exhibit very high density levels by designing the FETs to be very small so that the FETs and bit lines are closely placed together in the array.
Another type of solid state structure that may be used to store binary signals is the gate array. The gate array is a versatile logic IC which may be hardwire-programmed to perform a desired logic function and thus provide a higher level of functionality than the ROM. In essence, the gate array also has an array-type structure similar to the ROM 100 illustrated in FIG. 1, except that each gate array site is typically much larger than the site 111 in the ROM 100, because each gate array site will typically include several transistors and/or even a small logic processing unit with multiple input and output lines for each site.
Although the gate array is typically used to implement logic functions, a portion of a gate array may be used to implement a ROM by programming 2 bits into each site of the gate array using two n-channel transistors in each site. Each transistor may be programmed to connect or not connect with a single corresponding bit line.
Having discussed the density aspect of existing programmable storage circuits, the speed at which the stored signals may be read is also of importance. Referring to FIG. 1, the bit line 119 is attached (when so programmed) to the diffusion region (either the source or the drain, depending upon the supply voltages used) of the FET 118. Statistically, approximately one half of the FETs in a column may be coupled to the bit line after being programmed. Since ROM 100 may have thousands of wordlines, it is not unusual to have several thousand diffusion region couplings to the bit line 119. Since each coupling 117 adds capacitance to the bit line 119, the total capacitance on bit line 119 may be appreciable as compared to the discharging ability of a FET 118, such that discharging the bit line 119 through a single FET 118 will present a measurable delay while reading out the stored information from the ROM 100. Such a delay increases when thousands of wordlines are being selected sequentially. Therefore, given the above discussion concerning the operation of prior art storage circuits, an improvement in their speed and density is desirable.